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MAX8930
WLED Charge Pump, RGB, OLED Boost,
LDOs with ALC and CAI
The ambient light level at which the key backlight is
turned off can be set in register 0Fh. The default ambi-
ent light level is Ah, which is bright enough for the user
to recognize the numbers on the keypad. At this time,
the key output is held off. There is also a programmable
hysteresis level, accessed through I 2 C in the 0Fh regis-
ter. The default hysteresis width is 3h. The key output is
held high on any hysteresis value minus 1h. For example,
if the hysteresis is set to 3h, in this default condition, the
key output is held low at Ah level and then high at 6h level.
Keypad Backlight ON/OFF Operation by PWM
There is a built-in PWM signal operating at a frequency
of 500Hz. The on/off can be adjusted by duty cycle ratio
(set KYDT_ bit in Register 0Eh). 16 different duty values
of PWM are available in register 0Eh. In addition, fade-in
and fade-out can also be set up with the KYSL_ bits in
the 0Eh register.
Keypad Backlight ON/OFF Operation
by I 2 C Command
There is a dedicated register bit (KYI2C at 02h, see
Table 15) to both enable and disable the KEY function.
This I 2 C on/off is the default for KEY.
Control of Duty Transition Time Control
in Internal PWM Mode (500Hz)
The internal 500Hz PWM can set up the duty transition
control time by the register (KYSL1 and KYSL2 at 0Eh).
Figure 8 shows the duty transition in slope-applied mode.
Low-Drop Output (LDO) Operation
The linear regulators are designed for low-input, low-
dropout, low quiescent current to maximize battery life.
TARGET DUTY VALUE
All LDOs are controlled through the serial interface, mini-
mizing the requirements of control lines to the MAX8930.
Each of the LDOs are turned on or off through the setting
of the control bits in the On/Off Control register, 00h. For
each LDO, it is possible to set the output voltage and
enable/disable the active pulldown resistor (1k I typ)
during power-off. This is done in the 03h and 04h reg-
isters. For optimized battery life, there are two external
supply voltage inputs, PV3 for LDO1 and LDO2 and PV4
for LDO3. This allows the input voltage of the LDO to
be supplied from a lower voltage power rail, resulting in
higher efficiency operation and longer battery life. LDO3
is a low V IN LDO (V IN = 1.7V to 5.5V). The input voltage,
V PV3 and V PV4 must be greater than the selected LDO1
to LDO3 voltages.
GPO Operation
Three LDO outputs have the option of being converted to
GPO outputs through an I 2 C command. Figure 9 shows
the external connections. The register, 24h, is respon-
sible for this setup. In GPO mode, the output capacitors
should be removed in advance, otherwise, there is some
delay in both turn-on and turn-off mode.
Component Selection
Use only ceramic capacitors with an X5R, X7R, or bet-
ter dielectric. See the Table 6 for a list of recommended
parts. Connect a 1 F F and 2.2 F F ceramic capacitor
between LDO1, LDO2, and LDO3 and PGND3, respec-
tively, for 200mA applications. The LDO output capaci-
tor’s equivalent series resistance (ESR) affects stability
and output noise. Use output capacitors with an ESR
of 0.1 I or less to ensure stability and optimum transient
I/O VOLTAGE
SLOPE TIME
LDO1
LDO2
LDO3
LDO1
LDO2
LDO3
OUTPUT
OUTPUT
OUTPUT
TIME
Figure 8. Slope Time-In Internal PWM Mode (500Hz)
30
Figure 9. LDO GPO Configuration
Maxim Integrated
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